Chip embedding technology, for example, in the field of semiconductor chip-package construction, places high requirements on the individual processes of creating a package. Difficulties may arise during the die attach process, for example with respect to x-y tolerances, leadframe deflection, and bond line thicknesses. Further difficulties may arise in the deposition of source/drain and gate contacts, for example during the fabrication of power semiconductor devices. Further difficulties may arise during sawing processes for module individualization. Sawing through a combination of materials, ranging from, for example, resin for embedding materials, to, for example copper leadframes, may introduce saw edges and impurities. For a package to be individualized, a large area of copper, which may be part of a copper leadframe, is typically processed during the process chain, and therefore a large portion of the leadframe must be removed by etching techniques.
In addition to the difficulties of the process control and yield losses, high costs for the development of current chip-embedding technologies, and increasing manufacturing costs due to the application of a large area copper carrier may add to difficulties for a possible launch in the semiconductor market.